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FEATURES Complete 12-Bit I/O System, Comprising: 12-Bit ADC with Track/Hold Amplifier 83 kHz Throughout Rate 72 dB SNR 12-Bit DAC with Output Amplifier 3 s Settling Time 72 dB SNR On-Chip Voltage Reference Operates from 5 V Supplies Low Power - 130 mW typ Small 0.3" Wide DIP APPLICATIONS Digital Signal Processing Speech Recognition and Synthesis Spectrum Analysis High Speed Modems DSP Servo Control
LC2MOS Complete, 12-Bit Analog I/O System AD7868
FUNCTIONAL BLOCK DIAGRAM
VDD RI DAC R R
LDAC TFS TCLK DT CONTROL RFS RCLK DR CLK CONVST CLOCK
12-BIT DAC DAC 3V REFERENCE ADC 3V REFERENCE ADC SERIAL INTERFACE R 12-BIT ADC R
VOUT
DAC SERIAL INTERFACE
RO DAC
RO ADC
VIN TRACK/HOLD
AD7868
GENERAL DESCRIPTION
DGND
VSS
AGND
The AD7868 is a complete 12-bit I/O system containing a DAC and an ADC . The ADC is a successive approximation type with a track-and-hold amplifier having a combined throughput rate of 83 kHz. The DAC has an output buffer amplifier with a settling time of 3 s to 12 bits. Temperature compensated 3 V buried Zener references provide precision references for the DAC and ADC. Interfacing to both the DAC and ADC is serial, minimizing pin count and giving a small 24-pin package size. Standard control signals allow serial interfacing to most DSP machines. Asynchronous ADC conversion control and DAC updating is made possible with the CONVST and LDAC logic inputs. The AD7868 operates from 5 V power supplies, the analog input/output range of the ADC/DAC is 3 V. The part is fully specified for dynamic parameters such as signal-to-noise ratio and harmonic distortion as well as traditional dc specifications. The part is available in a 24-pin, 0.3" wide, plastic or hermetic dual-in-line package (DIP) and in a 28-pin, plastic SOIC package.
PRODUCT HIGHLIGHTS
1. Complete 12-Bit I/O System. The AD7868 contains a 12-bit ADC with a track-and-hold amplifier and a 12-bit DAC with output amplifier. Also included are separate on-chip voltage references for the DAC and the ADC. 2. Dynamic Specifications for DSP Users. In addition to traditional dc specifications, the AD7868 is specified for ac parameters including signal-to-noise ratio and harmonic distortion. These parameters along with important timing parameters are tested on every device. 3. Small Package. The AD7868 is available in a 24-pin DIP and a 28-pin SOIC package.
REV. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. (c) Analog Devices, Inc., 1996 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703
AD7868-SPECIFICATIONS 5%, AGND = DGND = 0 V, f (V = +5 V 5%, V = -5 V
ADC SECTION
DD SS
CLK
= 2.0 MHz external. All specifications TMIN to TMAX-
unless otherwise noted.)
A Version1
2
Parameter DYNAMIC PERFORMANCE Signal-to-Noise Ratio3, 4 (SNR) @ +25C TMIN to TMAX Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise Intermodulation Distortion (IMD) Second Order Terms Third Order Terms Track/Hold Acquisition Time DC ACCURACY Resolution Minimum Resolution Integral Nonlinearity Integral Nonlinearity Differential Nonlinearity Bipolar Zero Error Positive Gain Error5 Negative Gain Error5 ANALOG INPUT Input Voltage Range Input Current REFERENCE OUTPUT6 RO ADC @ +25C RO ADC TC RO ADC TC Reference Load Sensitivity (RO ADC vs. I)
B Version1 72 71 -78 -78 -78 -80 2 12 12 12 1 0.9 5 5 5 3 1
T Version1 70 70 -76 -76 -76 -78 2 12 12 12 1 0.9 5 5 5 3 1
Units dB min dB min dB max dB max dB max dB max s max Bits Bits LSB typ LSB max LSB max LSB max LSB max LSB max Volts mA max V min/V max ppm/C typ ppm/C max mV max
Test Conditions/Comments VIN = 10 kHz Sine Wave, fSAMPLE = 83 kHz Typically 71.5 dB for 0 < VIN < 41.5 kHz VIN = 10 kHz Sine Wave, fSAMPLE = 83 kHz Typically 71.5 dB for 0 < VIN < 41.5 kHz VIN = 10 kHz Sine Wave, fSAMPLE = 83 kHz Typically 71.5 dB for 0 < VIN < 41.5 kHz fa = 9 kHz, fb = 9.5 kHz, fSAMPLE = 50 kHz fa = 9 kHz, fb = 9.5 kHz, fSAMPLE = 50 kHz
70 70 -78 -78 -78 -80 2 12 12 12 0.9 5 5 5 3 1
No Missing Codes Are Guaranteed
2.99/3.01 2.99/3.01 2.99/3.01 25 25 25 40 50 -1.5 -1.5 -1.5
Reference Load Current Change (0 A-500 A), Reference Load Should Not Be Changed During Conversion VDD = 5 V 5% VDD = 5 V 5% VIN = 0 V to VDD VIN = VSS to DGND
LOGIC INPUTS (CONVST, CLK, CONTROL) Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Current7 (CONTROL Input Only) Input Capacitance, CIN8 LOGIC OUTPUTS DR, RFS Outputs Output Low Voltage, VOL RCLK Output Output Low Voltage, VOL DR, RFS, RCLK Outputs Floating-State Leakage Current Floating-State Output Capacitance8 CONVERSION TIME External Clock Internal Clock POWER REQUIREMENTS VDD VSS IDD ISS Total Power Dissipation
2.4 0.8 10 10 10
2.4 0.8 10 10 10
2.4 0.8 10 10 10
V min V max A max A max pF max
0.4 0.4 10 15 10 10 +5 -5 22 12 170
0.4 0.4 10 15 10 10 +5 -5 22 12 170
0.4 0.4 10 15 10 10 +5 -5 25 13 190
V max V max A max pF max s max s max V nom V nom mA max mA max mW max
ISINK = 1.6 mA, Pull-Up Resistor = 4.7 k ISINK = 2.6 mA, Pull-Up Resistor = 2 k
The Internal Clock Has a Nominal Value of 2.0 MHz For Both DAC and ADC 5% for Specified Performance 5% for Specified Performance Cumulative Current from the Two VDD Pins Cumulative Current from the Two VSS Pins Typically 130 mW
NOTES 1 Temperature ranges are as follows: A/B Versions, -40C to +85C; T Version, -55C to +125C. 2 VIN = 3 V 3 SNR calculation includes distortion and noise components. 4 SNR degradation due to asynchronous DAC updating during conversion is 0.1 dB typ. 5 Measured with respect to internal reference. 6 For capacitive loads greater than 50 pF a series resistor is required (see INTERNAL REFERENCE section). 7 Tying the CONTROL input to V DD places the device in a factory test mode where normal operation is not exhibited. 8 Sample tested @ +25C to ensure compliance. Specifications subject to change without notice.
-2-
REV. B
AD7868 DAC SECTION
Parameter DYNAMIC PERFORMANCE Signal-to-Noise Ratio3 (SNR) @ +25C TMIN to TMAX Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise DC ACCURACY Resolution Integral Nonlinearity Integral Nonlinearity Differential Nonlinearity Bipolar Zero Error Positive Full-Scale Error5 Negative Full-Scale Error5 REFERENCE OUTPUT6 RO ADC @ +25C RO ADC TC RO ADC TC Reference Load Change (RO DAC vs. I) REFERENCE INPUT RI DAC Input Range Input Current LOGIC INPUTS (LDAC, TFS, TCLK, DT) Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN7 ANALOG INPUT Output Voltage Range dc Output Impedance Short-Circuit Current AC CHARACTERISTICS7 Voltage Output Settling-Time Positive Full-Scale Change Negative Full-Scale Change Digital-to-Analog Glitch Impulse Digital Feedthrough VIN to VOUT Isolation POWER REQUIREMENTS
2
(VDD = +5 V 5%, VSS = -5 V 5%, AGND = DGND = 0 V, RI DAC = +3 V and decoupled as shown in Figure 2, VOUT Load to AGND; RL = 2 k, CL = 100 pF. All specifications TMIN to TMAX unless otherwise noted.)
A Version1 70 70 -78 -78 B Version1 72 71 -78 -78 T Version1 70 70 -76 -76 Units dB min dB min dB max dB max Test Conditions/Comments VOUT = 1 kHz Sine Wave, fSAMPLE = 83 kHz Typically 71.5 dB at +25C for 0 < VOUT < 20 kHz4 VOUT = 1 kHz Sine Wave, fSAMPLE = 83 kHz Typically -84 dB at +25C for 0 < VOUT < 20 kHz4 VOUT = 1 kHz Sine Wave, fSAMPLE = 83 kHz Typically -84 dB at +25C for 0 < VOUT < 20 kHz4
12 1/2 0.9 5 5 5
12 1/2 1 0.9 5 5 5
12 1/2 1 0.9 5 5 5
Bits LSB typ LSB max LSB max LSB max LSB max LSB max
Guaranteed Monotonic
2.99/3.01 2.99/3.01 2.99/3.01 25 25 25 40 50 -1.5 -1.5 -1.5 2.85/3.15 2.85/3.15 2.85/3.15 1 1 1 2.4 0.8 10 10 3 0.3 20 2.4 0.8 10 10 3 0.3 20 2.4 0.8 10 10 3 0.3 20
V min/V max ppm/C typ ppm/C max mV max Reference Load Current Change (0-500 A) V min/V max 3 V 5% A max V min V max A max pF max V nom typ mA typ Settling Time to Within 1/2 LSB of Final Value Typically 2 s Typically 2.5 s DAC Code Change All 1s to All 0s VIN = 3 V, 41.5 kHz Sine Wave VDD = 5 V 5% VDD = 5 V 5% VIN = 0 V to VDD
3 3 10 2 100
3 3 10 2 100
3 3 10 2 100
s max s max nV secs typ nV secs typ dB typ
As per ADC Section
NOTES 1 Temperature ranges are as follows: A/B Versions, -40C to +85C; T Version, -55C to +125C. 2 VOUT (pk-pk) = 3 V. 3 SNR calculation includes distortion and noise components. 4 Using external sample and hold. 5 Measured with respect to RI DAC and includes bipolar offset error. 6 For capacitive loads greater than 50 pF a series resistor is required (see INTERNAL REFERENCE section). 7 Sample tested @ +25C to ensure compliance. Model Specifications subject to change without notice.
ORDERING GUIDE
Temperature Range
-40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C
SNR
70 dB 70 dB 72 dB 72 dB 70 dB 72 dB
Relative Accuracy (LSB)
1/2 typ 1/2 typ 1 max 1 max 1/2 typ 1 max
Package Option*
N-24 Q-24 N-24 Q-24 R-28 R-28
AD7868AN AD7868AQ AD7868BN AD7868BQ AD7868AR AD7868BR
*N = Plastic DIP; Q = Cerdip; R = SOIC (Small Outline IC).
REV. B
-3-
AD7868 TIMING CHARACTERISTICS1, 2 (V
Parameter ADC TIMING t1 t2 3 t3 t4 t5 4 t6 t135 DAC TIMING t7 t8 t9 6 t10 t11 t12 Limit at TMIN, TMAX (A, B Versions) 50 440 100 20 100 155 4 100 2 RCLK +200 to 3 RCLK + 200 50 75 150 30 75 40
DD
= +5 V
5%, VSS = -5 V
5%, AGND = DGND = 0 V)
Units ns min ns min ns min ns min ns max ns max ns min ns max ns typ Conditions/Comments CONVST Pulse Width RCLK Cycle Time, Internal Clock RFS to RCLK Falling Edge Setup Time RCLK Rising Edge to RFS RCLK to Valid Data Delay, CL = 35 pF Bus Relinquish Time after RCLK CONVST to RFS Delay
Limit at TMIN, TMAX (T Version) 50 440 100 20 100 155 4 100 2 RCLK +200 to 3 RCLK + 200 50 100 200 40 100 40
ns min ns min ns min ns min ns min ns min
TFS to TCLK Falling Edge TCLK Falling Edge to TFS TCLK Cycle Time Data Valid to TCLK Setup Time Data Valid to TCLK Hold Time LDAC Pulse Width
NOTES 1 Timing specifications are sample tested at +25C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. 2 Serial timing is measured with a 4.7 k pull-up resistor on DR and RFS and a 2 k pull-up resistor on RCLK . The capacitance on all three output is 35 pF. 3 When using internal clock, RCLK mark/space ratio (measured from a voltage level of 1.6 V) range is 40/60 to 60/40. For external clock, RCLK mark/space ratio = external clock mark/space ratio. 4 DR will drive higher capacitance loads but this will add to t 5 since it increases the external RC time constant (4.7 k/CL) and hence the time to reach 2.4 V. 5 Time 2 RCLK to 3 RCLK depends on conversion start to ADC clock synchronization. 6 TCLK mark/space ratio is 40/60 to 60/40.
ABSOLUTE MAXIMUM RATINGS*
(TA = +25C unless otherwise noted)
PIN CONFIGURATIONS DIP
CONVST CLK RFS RCLK DR DGND VDD AGND VOUT 1 2 3 4 5 6 7 8 9 24 CONTROL 23 VDD 22 VSS 21 VIN 20 RO ADC
CONVST CLK RFS NC RCLK 1 2 3 4 5 6 7 8 9
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V VSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to -7 V AGND to DGND . . . . . . . . . . . . . . . . . -0.3 V to VDD +0.3 V VOUT to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS to VDD VIN to AGND . . . . . . . . . . . . . . . . VSS -0.3 V to VDD + 0.3 V RO ADC to AGND . . . . . . . . . . . . . . . -0.3 V to VDD + 0.3 V RO DAC to AGND . . . . . . . . . . . . . . . -0.3 V to VDD + 0.3 V RI DAC to AGND . . . . . . . . . . . . . . . -0.3 V to VDD + 0.3 V Digital Inputs to AGND . . . . . . . . . . . -0.3 V to VDD + 0.3 V Digital Outputs to AGND . . . . . . . . . . -0.3 V to VDD + 0.3 V Operating Temperature Range A, B Versions . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C T Version . . . . . . . . . . . . . . . . . . . . . . . . . -55C to +125C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300C Power Dissipation (Any Package) to +75C . . . . . . . . 450 mW Derates above +75C by . . . . . . . . . . . . . . . . . . . . 10 mW/C
*Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
SOIC
28 27 26 25 24 23 CONTROL VDD VSS NC VIN RO ADC AGND DGND TCLK NC NC DT TFS LDAC
AD7868
TOP VIEW (Not to Scale)
19 AGND 18 NC
DR DGND VDD
AD7868
TOP VIEW (Not to Scale)
22 21 20 19 18 17 16 15
17 DGND
AGND
16 TCLK 15 DT 14 TFS 13 LDAC NC = NO CONNECT
VOUT 10 NC 11 VSS 12 RO DAC 13
VSS 10 RO DAC 11 RI DAC 12
RI DAC 14 NC = NO CONNECT
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7868 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
-4-
REV. B
AD7868
PIN FUNCTION DESCRIPTION
DIP Pin Number
Mnemonic
Function Positive Power Supply, 5 V 5%. Both VDD pins must be tied together. Negative Power Supply, -5 V 5%. Both VSS pins must be tied together. Analog Ground. Both AGND pins must be tied together. Digital Ground. Both DGND pins must be tied together.
POWER SUPPLY 7 & 23 VDD 10 & 22 VSS 8 & 19 AGND 6 &17 DGND
ANALOG SIGNAL AND REFERENCE 21 VIN ADC Analog Input. The ADC input range is 3 V. 9 VOUT Analog Output Voltage from DAC. This output comes from a buffer amplifier. The range is bipolar, 3 V with RI DAC = +3 V. 20 RO ADC Voltage Reference Output. The internal ADC 3 V reference is provided at this pin. This output may be used as a reference for the DAC by connecting it to the RI DAC input. The external load capability of this reference is 500 A. 11 RO DAC DAC Voltage Reference Output. This is one of two internal voltage references. To operate the DAC with this internal reference, RO DAC should be connected to RI DAC. The external load capability of the reference is 500 A. 12 RI DAC DAC Voltage Reference Input. The voltage reference for the DAC must be applied to this pin. It is internally buffered before being applied to the DAC. The nominal reference voltage for correct operation of the AD7868 is 3 V. ADC INTERFACE AND CONTROL 2 CLK Clock Input. An external TTL-compatible clock may be applied to this input. Alternatively, tying pin to VSS enables the internal laser-trimmed oscillator. RFS Receive Frame Synchronization, Logic Output. This is an active low open-drain output which provides 3 a framing pulse for serial data. An external 4.7 k pull-up resistor is required on RFS. 4 RCLK Receive Clock, Logic Output. RCLK is the gated serial clock output which is derived from the internal or external ADC clock. If the CONTROL input is at VSS the clock runs continuously. With the CONTROL input at DGND the RCLK output is gated off (three-stated) after serial transmission is complete. RCLK is an open-drain output and requires an external 2 k pull-up resistor. 5 DR Receive Data, Logic Output. This is an open-drain data output used in conjunction with RFS and RCLK to transmit data from the ADC. Serial data is valid on the falling edge of RCLK when RFS is low. An external 4.7 k resistor is required on the DR output. 1 CONVST Convert Start, Logic Input. A low to high transition on this input puts the track-and-hold amplifier into the hold mode and starts an ADC conversion. This input in asynchronous to the CLK input. 24 CONTROL Control, Logic Input. With this pin at 0 V, the RCLK is noncontinuous. With this pin at -5 V, the RCLK is continuous. Note, tying this pin to VDD places the part in a factory test mode where normal operation is not exhibited. DAC INTERFACE AND CONTROL 14 TFS Transmit Frame Synchronization, Logic Input. This is a frame or synchronization signal for the DAC with serial data expected after the falling edge of this signal. 15 DT Transmit Data, Logic Input. This is the data input which is used in conjunction with TFS and TCLK to transfer serial data to the input latch. 16 TCLK Transmit Clock, Logic Input. Serial data bits are latched on the falling edge of TCLK when TFS is low. LDAC Load DAC, Logic Input. A new word is transferred into the DAC latch from the input latch on the 13 falling edge of this signal. 18 NC No Connect.
REV. B
-5-
AD7868
CONVERTER DETAILS
The AD7868 is a complete 12-bit I/O port, the only external components required for normal operation are pull-up resistors for the ADC data outputs and power supply decoupling capacitors. It is comprised of a 12-bit successive approximation ADC with a track/hold amplifier, a 12-bit DAC with a buffered output and two 3 V buried Zener references, a clock oscillator and control logic.
ADC CLOCK
The operation of the track/hold amplifier is essentially transparent to the user. The track/hold amplifier goes from its track mode to its hold mode at the start of conversion on the rising edge of CONVST.
INTERNAL REFERENCES
The AD7868 has an internal clock oscillator which can be used for the ADC conversion procedure. The oscillator is enabled by tying the CLK input to VSS. The oscillator in laser trimmed at the factory to give a conversion time of between 8.5 and 10 s. The mark/space ratio can vary from 40/60 to 60/40. Alternatively, an external TTL compatible clock may be applied to this input. The allowable mark/space ratio of an external clock is 40/60 to 60/40. RCLK is a clock output, used for the serial interface. This output is derived directly from the ADC clock source and can be switched off at the end of conversion with the CONTROL input.
ADC CONVERSION TIMING
The AD7868 has two on-chip temperature compensated buried Zener references which are factory trimmed to 3 V 10 mV. One reference provides the appropriate biasing for the ADC, while the other is available as a reference of the DAC. Both reference outputs are available (labeled RO DAC and RO ADC) and are capable of providing up to 500 A to an external load. The DAC input reference (RI DAC) can be stored externally or connected to any of the two on-chip references. Applications requiring good full-scale error matching between the DAC and the ADC should use the ADC reference as shown in Figure 4. The maximum recommended capacitance on either of the reference output pins for normal operation is 50 pF. If either of the reference outputs is required to drive a capacitive load greater than 50 pF, then a 200 resistor must be placed in series with the capacitive load. The addition of decoupling capacitors, 10 F in parallel with 0.1 F, as shown in Figure 2, improves noise performance. The improvement in noise performance can be seen from the graph in Figure 3. Note, this applies for the DAC output only; reference decoupling components do not affect ADC performance. So, a typical application will have just the DAC reference source decoupled with the other one open circuited.
RO DAC or RO ADC* 200 EXT LOAD GREATER THAN 50pF 10F 0.1F
The conversion time for both external clock and continuous internal clock can vary from 19 to 20 rising clock edges depending on the conversion start to ADC clock synchronization. If a conversion is initiated within 30 ns prior to a rising edge of the ADC clock, the conversion time will consist of 20 rising clock edges, i.e., 9.5 s conversion time. For noncontinuous internal clock, the conversion time is always 19 rising clock edges.
ADC TRACK-AND-HOLD AMPLIFIER
The track-and-hold amplifier on the analog input of the AD7868 allows the ADC to accurately convert an input sine wave of 6 V peak-peak amplitude to 12-bit accuracy. The input impedance is typically 9 k, an equivalent circuit is shown in Figure 1. The input bandwidth of the track/hold amplifier is much greater than the Nyquist rate of the ADC, even when the ADC is operated at its maximum throughput rate. The 0.1 dB cutoff frequency occurs typically at 500 kHz. The track/hold amplifier acquires an input signal to 12-bit accuracy in less than 2 s.
RI DAC
*RO DAC/RO ADC CAN BE LEFT OPEN CIRCUIT IF NOT USED
Figure 2. Reference Decoupling Circuitry
DAC OUTPUT AMPLIFIER
TRACK/HOLD AMPLIFIER 4.5k VIN TO INTERNAL COMPARATOR
4.5k
AD7868*
TO INTERNAL 3V REFERENCE
The output from the voltage-mode DAC is buffered by a noninverting amplifier. The buffer amplifier is capable of developing 3 V across 2 k and 100 pF load to ground and can produce 6 V peak-to-peak sine wave signals to a frequency of 20 kHz. The output is updated on the falling edge of the LDAC input. The output voltage settling time, to within 1/2 LSB of its final value, is typically less than 2 s. The small signal (200 mV p-p) bandwidth of the output buffer amplifier is typically 1 MHz. The output noise from the amplifier is low with a figure of 30 nV/Hz at a frequency of 1 kHz. The broadband noise from the amplifier exhibits a typical peakto-peak figure of 150 V for a 1 MHz output bandwidth. Figure 3 shows a typical plot of noise spectral density versus frequency for the output buffer amplifier and for either of the on-chip references.
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 1. ADC Analog Input
The overall throughput rate is equal to the conversion time plus the track/hold amplifier acquisition time. For a 2.0 MHz input clock the throughput time is 12 s max.
-6-
REV. B
AD7868
500 TA = +25C VDD = +5V 200 VSS = -5V
the input signal is within the full dynamic range of the ADC. For applications which require that the input signal range match the full analog input dynamic range of the ADC, offset and full-scale errors have to be adjusted to zero.
ADC ADJUSTMENT
100
nV - Hz
REF OUT
50
DAC OUTPUT WITH ALL 0s LOADED REF OUT DECOUPLED AS SHOWN IN FIGURE 2
20
10 50
100
200
1k
2k
10k
20k
100k
FREQUENCY - Hz
Figure 6 has signal conditioning at the input and output of the AD7868 for trimming the end points of the transfer functions of both the ADC and the DAC. Offset error must be adjusted before full-scale error. For the ADC, this is achieved by trimming the offset of A1 while the input voltage, V1, is 1/2 LSB below ground. The trim procedure is as follows: apply a voltage of -0.73 mV (-1/2 LSB) at V1 in Figure 6 and adjust the offset voltage of A1 until the ADC output code flickers between 1111 1111 1111 (FFF HEX) and 0000 0000 0000 (000 HEX). ADC gain error can be adjusted at either the first code transition (ADC negative full scale) or the last code transition (ADC positive full scale). The trim procedures for both cases are as follows (see Figure 6).
ADC Positive Full-Scale Adjustment
Figure 3. Noise Spectral Density vs. Frequency
INPUT/OUTPUT TRANSFER FUNCTIONS
A bipolar circuit for the AD7868 is shown in Figure 4. The analog input/output voltage range of the AD7868 is 3 V. The designed code transitions for the ADC occur midway between successive integer LSB values (i.e., 1/2 LSB, 3/2 LSB, 5/2 LSB . . . FS - 3/2 LSBs). The input/output code is 2s complement binary with 1 LSB = FS/4096 = 1.46 mV. The ideal transfer function is shown in Figure 5.
AD7868*
VIN ANALOG INPUT RANGE = 3V R1 200 RO ADC C1 10F C2 0.1F AGND VOUT RI DAC
Apply a voltage of 2.9978 V (FS/2 - 3/2 LSBs) at V1. Adjust R2 until the ADC output code flickers between 0111 1111 1110 (7FE HEX) and 0111 1111 1111 (7FF HEX).
ADC Negative Full-Scale Adjustment
ANALOG OUTPUT RANGE = 3V
Apply a voltage of -2.9993 V (-FS/2 + 1/2 LSB) at V1 and adjust R2 until the ADC output code flickers between 1000 0000 0000 (800 HEX) and 1000 0000 0001 (801 HEX).
DAC ADJUSTMENT
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 4. AD7868 Basic Bipolar Operation Using RO ADC as a Reference Input for the DAC
OUTPUT CODE
Op amp A2 is included in Figure 6 for the DAC transfer function adjustment. Again offset must be adjusted before full scale. To adjust offset: load the DAC with 0000 0000 0000 (000 HEX) and trim the offset of A2 to 0 V. As with the ADC adjustment, gain error can be adjusted at either the first code transition (DAC negative full scale) or the last code transition (DAC positive full scale). The trim procedures for both cases are as follows:
DAC Positive Full-Scale Adjustment
011...111 011...110
Load the DAC with 0111 1111 1111 (7FF HEX) and adjust R7 until the op amp output voltage is equal to 2.9985 V, (FS/2 - 1 LSB).
DAC Negative Full-Scale Adjustment
-FS 2
+ FS
000...010 000...001 000...000 111...111 111...110
Load the DAC with 1000 0000 0000 (800 HEX) and adjust R7 until the op amp output voltage is equal to 3.0 V (-FS/2).
-1LSB
V1 INPUT VOLTAGE RANGE = 3V
2
FS = 6V 1LSB = FS 4096
R1 10k R2 500
100...001 100...000
A1
VIN
VOUT R6 10k R7 500 R8 10k V0 OUTPUT VOLTAGE RANGE = 3V
0V INPUT VOLTAGE
R3 10k R5 10k
R4 10k
AD7868*
Figure 5. AD7868 Input/Output Transfer Function
OFFSET AND FULL-SCALE ADJUSTMENT
AGND
A2
In most digital signal processing (DSP) applications, offset and full-scale errors have little or no effect on system performance. Offset error can always be eliminated in the analog domain by ac coupling. Full-scale errors do not cause problems as long as REV. B -7-
*ADDITIONAL PINS OMITTED FOR CLARITY
R10 10k
R9 10k
Figure 6. AD7868 with Input/Output Adjustment
AD7868
TIMING AND CONTROL
Communication with the AD7868 is managed by 6 dedicated pins. These consist of separate serial clocks, word framing or strobe pulses and data signals for both receiving and transmitting data. Conversion starts and DAC updating are controlled by two digital inputs; CONVST and LDAC. These inputs can be asserted independently of the microprocessor by an external timer when precise sampling intervals are required. Alternatively, the LDAC and CONVST can be driven from a decoded address bus allowing the microprocessor control over conversion start and DAC updating as well as data communication to the AD7868.
ADC Timing
serial clock which runs continuously. Both options are available on the AD7868 ADC. With the CONTROL input at 0 V, RCLK is noncontinuous and when it is at -5 V, RCLK is continuous.
DAC Timing
The AD7868 DAC contains two latches, an input latch and a DAC latch. Data must be loaded to the input latch under the control of the TCLK, TFS and DT serial logic inputs. Data is then transferred from the input latch to the DAC latch under the control of the LDAC signal. Only the data in the DAC latch determines the analog output of the AD7868. Data is loaded to the input latch under control of TCLK, TFS and DT. The AD7868 DAC expects a 16-bit stream of serial data on its DT input. Data must be valid on the falling edge of TCLK. The TFS input provides the frame synchronization signal which tells the AD7868 DAC that valid serial data will be available for the next 16 falling edges of TCLK. Figure 8 shows the timing diagram for the serial data format. Although 16 bits of data are clocked into the input latch, only 12 bits are transferred into the DAC latch. Therefore, 4 bits in the stream are don't cares since their value does not affect the DAC latch data. The bit positions are 4 don't cares followed by the 12-bit DAC data starting with the MSB. The LDAC signal controls the transfer of data to the DAC latch. Normally, data is loaded to the DAC latch on the falling edge of LDAC. However, if LDAC is held low, then serial data is loaded to the DAC latch on the sixteenth falling edge of TCLK. If LDAC goes low during the loading of serial data to the input latch, no DAC latch update takes place on the falling edge of LDAC. If LDAC stays low until the serial transfer is completed, then the update takes place on the sixteenth falling edge of TCLK. If LDAC returns high before the serial data transfer is completed, no DAC latch update takes place.
Conversion control is provided by the CONVST input. A low to high transition on CONVST input starts conversion and drives the track/hold amplifier into its hold mode. Serial data then becomes available while conversion is in progress. The corresponding timing diagram is shown in Figure 7. The word length is 16 bits; 4 leading zeros, followed by the 12-bit conversion result starting with the MSB. The data is synchronized to the serial clock output (RCLK) and is framed by the serial strobe (RFS). Data is clocked out on a low to high transition of the serial clock and is valid on the falling edge of this clock while the RFS output is low. RFS goes low at the start of conversion and the first serial data bit (which is the first leading zero) is valid on the first falling edge of RCLK. All the ADC serial lines are open-drain outputs and require external pull-up resistors. The serial clock out is derived from the ADC master clock source which may be internal or external. Normally, RCLK is required during the serial transmission only. In these cases it can be shut down (i.e., placed into high impedance) at the end of conversion to allow multiple ADCs to share a common serial bus. However, some serial systems (e.g., TMS32020) require a
t1
CONVST
CONVERSION TIME
t13
RFS 1
t3
RCLK
2, 3
t2
t4
t5
DR
1
t6
DB10 DB9 DB1 DB0
DB11
NOTES 1EXTERNAL 4.7k PULL-UP RESISTOR
2EXTERNAL
2k
PULL-UP RESISTOR
3CONTINUOUS
RCLK (DASHED LINE) WHEN THE CONTROL INPUT = -5V AND NONCONTINUOUS WHEN THE CONTROL INPUT = 0V
Figure 7. ADC Control Timing Diagram
t7
TFS
t8
t9
TCLK
t11 t10
DT DON'T DON'T DON'T DON'T CARE CARE CARE CARE DB11 DB10 DB1 DB0
Figure 8. DAC Control Timing Diagram
-8-
REV. B
AD7868
AD7868 DYNAMIC SPECIFICATIONS
The AD7868 is specified and 100% tested for dynamic performance specifications as well as traditional dc specifications such as integral and differential nonlinearity. These ac specifications are required for signal processing applications such as speech recognition, spectrum analysis, and high-speed modems. These applications require information on the converter's effect on the spectral content of the input signal. Hence, the parameters for which the AD7868 is specified include SNR, harmonic distortion and peak harmonics. These terms are discussed in more detail in the following sections.
Signal-to-Noise Ratio (SNR)
Figure 10 shows a typical plot of effective number of bits versus frequency for an AD7868BQ with a sampling frequency of 83 kHz. The effective number of bits typically falls between 11.7 and 11.85 corresponding to SNR figures of 72.2 and 73.1 dB.
SNR is the measured signal-to-noise ratio at the output of the ADC or DAC. The signal is the rms magnitude of the fundamental. Noise is the rms sum of all the nonfundamental signals up to half the sampling frequency (fs/2) excluding dc. SNR is dependent upon the number of levels used in the quantization process; the more levels, the smaller the quantization noise. The theoretical signal-to-noise ratio for a sine wave input is given by SNR = (6.02N + 1.76) dB where N is the number of bits. Thus for an ideal 12-bit converter, SNR = 74 dB.
Effective Number of Bits
12
(1)
Figure 9. AD7868, ADC FFT Plot
N=
SNR - 1.76 6.02
(2)
EFFECTIVE NUMBER OF BITS
The formula given in Equation 1 relates the SNR to the number of bits. Rewriting the formula, as in Equation 2, it is possible to get a measure of performance expressed in effective number of bits (N).
11.5
11
The effective number of bits for a device can be calculated directly from its measured SNR.
Harmonic Distortion
10.5
SAMPLE FREQUENCY = 83 kHz TA = 25C
Harmonic distortion is the ratio of the rms sum of harmonics to the fundamental. For the AD7868, total harmonic distortion (THD) is defined as
THD = 20 log V 2 +V 3 +V 4 +V 5 +V 6 V1
2 2 2 2 2
10 0 INPUT FREQUENCY - kHz 41.5
Figure 10. Effective Number of Bits vs. Frequency for the ADC
DAC Testing
where V1 is the rms amplitude of the fundamental and V2, V3, V4, V5 and V6 are the rms amplitudes of the second through to the sixth harmonic. The THD is also derived from the FFT plot of the ADC or DAC output spectrum.
ADC Testing
The output spectrum from the ADC is evaluated by applying a sine-wave signal of very low distortion to the VIN input which is sampled at an 83 kHz sampling rate. A Fast Fourier Transform (FFT) plot is generated from which the SNR data can be obtained. Figure 9 shows a typical 2048 point FFT plot of the AD7868BQ ADC with an input signal of 10 kHz and a sampling frequency of 83 kHz. The SNR obtained from this graph is 73 dB. It should be noted that the harmonics are taken into account when calculating the SNR.
A simplified diagram of the method used to test the dynamic performance specifications of the DAC is outlined in Figure 11. Data is loaded to the DAC under control of the microcontroller and associated logic. The output of the DAC is applied to a 9th order low-pass filter whose cutoff frequency corresponds to the Nyquist limit. The output of the filter is in turn applied to a 16-bit accurate digitizer. This digitizes the signal and the microcontroller generates an FFT plot from which the dynamic performance of the DAC can be evaluated.
REV. B
-9-
AD7868
MICROCONTROLLER AD7868 DAC LOW-PASS FILTER 16-BIT DIGITIZER
quencies at an update rate of 83 kHz. The plot of Figure 14 is without a sample-and-hold on the DAC output while the plot of Figure 15 is generated with a sample-and-hold on the output.
R2 2k2
Figure 11. AD7868 DAC Dynamic Performance Test Circuit
ADG201HS
VOUT R1 2k2 S1 D1
C9 330pF
The digitizer sampling is synchronized with the DAC update rate to ease FFT calculations. The digitizer samples the DAC output after the output has settled to its new value. Therefore, if the digitizer were to sample the output directly it would effectively be sampling a dc value each time. As a result, the dynamic performance of the DAC would not be measured correctly. Using the digitizer directly on the DAC output would give better results than the actual performance of the DAC. Using a filter between the DAC and the digitizer means that the digitizer samples a continuously moving signal and the true dynamic performance of the AD7868 DAC output is measured. Figure 12 shows a typical 2048 point Fast Fourier Transform plot for the AD7868 DAC with an update rate of 83 kHz and an output frequency of 1 kHz. The SNR obtained from the graph is 73 dBs.
AD7868*
LDAC
AD711
IN1
LDAC
1s ONE Q SHOT DELAY
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 13. DAC Sample-and-Hold Circuit
80 70 60 50
SNR - dBs
40 30 20 TA = +25C 10 0
0
1
2 3 FREQUENCY - kHz
4
5
Figure 14. DAC Performance vs. Frequency (No Sampleand-Hold)
80 70 60
Figure 12. AD7868 DAC FFT Plot
50
Some applications will require improved performance versus frequency from the AD7868 DAC. In these applications, a simple sample-and-hold circuit such as that outlined in Figure 13 will extend the very good performance of the DAC to 20 kHz. Other applications will already have an inherent sample-and-hold function following the AD7868 DAC output. An example of this type of application is driving a switched-capacitor filter where the updating of the DAC is synchronized with the switched-capacitor filter. This inherent sample-and-hold function also extends the frequency range performance.
Performance versus Frequency
SNR - dBs
40 30 20 TA = +25C 10 0 0
5
10 FREQUENCY - kHz
15
20
The typical performance plots of Figures 14 and 15 show the AD7868's DAC performance over a wide range of input fre-
Figure 15. DAC Performance vs. Frequency (Sample-andHold)
-10-
REV. B
AD7868
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD7868 is via a serial bus that uses standard protocol compatible with DSP machines. The communication interface consists of separate transmit (DAC) and receive (ADC) sections whose operations can be either synchronous or asynchronous with respect to each other. Each section has a clock signal, a data signal and a frame or strobe pulse. Synchronous operation means that data is transmitted from the ADC and to the DAC at the same time. In this mode only one interface clock is needed and this has to be the ADC clock out, so RCLK must be connected to TCLK. For asynchronous operation, DAC and ADC data transfers are independent of each other, the ADC provides the receive clock (RCLK) while the transmit clock (TCLK) may be provided by the processor or the ADC or some other external clock source. Another option to be considered with serial interfacing is the use of a gated clock. A gated clock means that the device that is sending the data switches on the clock when data is ready to be transmitted and three states the clock output when transmission is complete. Only 16 clock pulses are transmitted with the first data bit getting latched into the receiving device on the first falling clock edge. Ideally, there is no need for frame pulses, however, the AD7868 DAC frame input (TFS) has to be driven high between data transmissions. The easiest method is to use RFS to drive TFS and use only synchronous interfacing. This avoids the use of interconnects between the processor and AD7868 frame signals. Not all processors have a gated clock facility, Figure 16 shows an example with the DSP56000. Table I below shows the number of interconnect lines between the processor and the AD7868 for the different interfacing options. The AD7868 has the facility to use different clocks for transmitting and receiving data. This option, however, only exists on some processors and normally just one clock (ADC clock) is used for all communication with the AD7868. For simplicity, all the interface examples in this data sheet use synchronous interfacing and use the ADC clock (RCLK) as an input for the DAC clock (TCLK). For a better understanding of each of these interfaces, consult the relevant processor data sheet.
Table I. Interconnect Lines for Different Interfacing Options No. of Interconnects Signals 4 5 or 6 RCLK, DR, DT and RFS (TCLK = RCLK, TFS = RFS) RCLK, DR, RFS, DT, TFS (TCLK = RCLK or P serial CLK) RCLK, DR and DT (TCLK = RCLK, TFS = RFS)
DSP56000 internal serial control registers have to be configured for a 16-bit data word with valid data on the first falling clock edge. Conversion starts and DAC updating are controlled by an external timer. Data transfers, which occur during ADC conversions, are between the processor receive and transmit shift registers and the AD7868's ADC and DAC. At the end of each 16-bit transfer the DSP56000 receives an internal interrupt indicating the transmit register is empty and the receive register is full.
TIMER CONVST LDAC CONTROL
+ 5V
AD7868*
4.7k 2k 4.7k RFS TFS
DSP56000
SC0
SCK SRD STD
RCLK DR DT TCLK
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 16. AD7868--DSP56000 Interface
AD7868--ADSP-2101/ADSP-2102 Interface
An interface which is suitable for the ADSP-2101 or the ADSP2102 is shown in Figure 17. The interface is configured for synchronous, continuous clock operation. The LDAC is tied low so the DAC gets updated on the sixteenth falling clock after TFS goes low. Alternatively LDAC may be driven from a timer as shown in Figure 16. As with the previous interface the processor receives an interrupt after reading or writing to the AD7868 and updates its own internal registers in preparation for the next data transfer.
TIMER CONVST
Configuration Synchronous Asynchronous*
CONTROL - 5V
ADSP-2101/ ADSP-2102
RFS SCLK DR
+ 5V
AD7868*
4.7k 2k 4.7k RFS RCLK DR
Synchronous Gated Clock
3
TFS
TFS TCLK
*5 LINES OF INTERCONNECT WHEN TCLK = RCLK 6 LINES OF INTERCONNECT WHEN TCLK = P SERIAL CLK
DT
DT
AD7868--DSP56000 Interface
Figure 16 shows a typical interface between the AD7868 and DSP56000. The interface arrangement is synchronous with a gated clock requiring only three lines of interconnect. The
LDAC *ADDITIONAL PINS OMITTED FOR CLARITY
Figure 17. AD7868--ADSP-2101/ADSP-2102 Interface
REV. B
-11-
AD7868
AD7868--TMS32020/TMS320C25 Interface
Figure 18 shows an interface which is suitable for the TMS32020/TMS320C25 processors. This interface is configured for synchronous, continuous clock operation. Note, the AD7868 will not interface correctly to these processors if the AD7868 is configured for a noncontinuous clock. Conversion starts and DAC updating are controlled by an external timer.
TIMER CONVST LDAC - 5V CONTROL
analog circuitry from digital noise. The circuit layout of Figures 22 and 23 have both analog and digital ground planes which are kept separated and only joined together at the AD7868 AGND pins.
NOISE
Keep the input signal leads to VIN and signal return leads from AGND as short as possible to minimize input noise coupling. In applications where this is not possible, use a shielded cable between the source and the ADC. Reduce the ground circuit impedance as much as possible since any potential difference in grounds between the signal source and the ADC appears as an error voltage in series with the input signal.
INPUT/OUTPUT BOARD
TMS32020 TMS320C25
FSR CLKR DR
+ 5V
AD7868*
4.7k 2k 4.7k RFS RCLK DR
Figure 19 shows an analog I/O board based on the AD7868. The corresponding printed circuit board (PCB) layout and silkscreen are shown in Figures 21 to 23. The analog input to the AD7868 is buffered with an AD711 op amp. There is a component grid provided near the analog input on the PCB which may be used for an antialiasing filter for the ADC or a reconstruction filter for the DAC or any other conditioning circuitry. To facilitate this option, there are two wire links (labeled LK1 and LK2) required on the analog input and output tracks. The board contains a SHA circuit which can be used on the output of the AD7868 DAC to extend the very good performance of the part over a wider frequency range. The increased performance from the SHA can be seen in Figures 14 and 15 of this data sheet. A wire link (labeled LK3) connects the board output to either the SHA output or directly to the AD7868 DAC output. There are three LDAC link options on the board; LDAC can be driven from an external source independent of CONVST, LDAC can be tied to CONVST or LDAC can be tied to GND. Choosing the latter option of tying LDAC to GND disables the SHA operation, and places the SHA permanently in the track mode. Microprocessor connections to the board are made by a 9-way D-type connector. The pinout is shown in Figure 20. The ADC's digital outputs are buffered with 74HC4050s. These buffers provide a higher current output capability for high capacitance loads or cables. Normally, these buffers are not required as the AD7868 will be sitting on the same board as the processor.
POWER SUPPLY CONNECTIONS
FSX CLKX DX
TFS TCLK DT
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 18. AD7868--TMS32020/TMS320C25 Interface
APPLICATION HINTS
Good printed circuit board (PCB) layout is as important as the circuit design itself in achieving high speed A/D performance. The AD7868's comparator is required to make bit decisions on an LSB size of 1.465 mV. To achieve this, the designer has to be conscious of noise both in the ADC itself and in the preceding analog circuitry. Switching mode power supplies are not recommended as the switching spikes will feed through to the comparator causing noisy code transitions. Other causes of concern are ground loops and digital feedthrough from microprocessors. These are factors which influence any ADC, and a proper PCB layout which minimizes these effects is essential for best performance.
LAYOUT HINTS
Ensure that the layout for the printed circuit board has the digital and analog signal lines separated as much as possible. Take care not to run any digital track alongside an analog signal track. Guard (screen) the analog input with AGND. Establish a single point analog ground (star ground) separate from the logic system ground as close as possible to the AD7868 AGND pins. Connect all other grounds and the AD7868 DGND to this single analog ground point. Do not connect any other digital grounds to this analog ground point. Low impedance analog and digital power supply common returns are essential to low noise operation of the ADC, so make the foil width for these tracks as wide as possible. The use of ground planes minimizes impedance paths and also guards the
The PCB requires two analog power supplies and one 5 V digital supply. Connections to the analog supply are made directly to the PCB as shown on the silkscreen in Figure 21. The connections are labeled V+ and V- and the range for both of these supplies is 12 V to 15 V. Connections to the 5 V digital supply are made through the D-type connector SKT6. The 5 V analog supply required by the AD7868 are generated from two voltage regulators on the V+ and V- supplies.
-12-
REV. B
AD7868
V+ 5V IN OUT IC5 78L05 GND C2 0.1F C1 10F V+ C5 10F ANALOG INPUT 3V RANGE A SKT1 C C6 0.1F
LK1 B + IC2 V- COMPONENT GRID
VDD
VDD R7 200
AD711
VIN RO ADC
RI DAC C7 10F C8 0.1F RO DAC
A B C
C24 0.1F LK4
C23 10F
IC1 AD7868
CONTROL COMPONENT GRID LK2 SKT2 A ANALOG OUTPUT 3V RANGE V+ C10 0.1F C9 10F LK3 B AGND B A C DGND DGND 5V
-5V A B C LK5
AGND SKT6 9-WAY D-TYPE CONNECTOR 5V DR DR RCLK
RCLK
C
R3 4.7k
R4 2k
R5 4.7k
IC7 1/2 74HC4050
AD711
IC3 V-
+
IC4 ADG201HS
R1 2k VOUT
RFS RFS LK9 LK8
C12 0.1F C21 330pF R2 2k
C11 10F
TFS TFS TCLK DT TCLK DT
DGND CLK
5V LDAC R6 15k C22 68pF CEXT B 5V C4 0.1F C A LK6 B C3 10F CLR VCC REXT /C EXT A -5V OUT IN V- Q CONVST VSS VSS A B LK7 -5V C
IC8 1/2 74HC221
GND
IC6 79L05
GND
SKT3 LDAC
SKT4 CONVST
SKT5 EXT CLK
Figure 19. Input/Output Circuit Based on the AD7868
TCLK RCLK
WIRE LINK OPTIONS LK1, Analog Input Link
RFS
DR
DT
1 6
2 7
3 8
4 9
5
LK1 connects the analog input to a component grid or to a buffer amplifier which drives the ADC input.
LK2, Analog Output Link
DGND
TFS
NC
5V
LK2 connects the analog output to the component grid or to either the SHA or DAC output (see LK3).
LK3, SHA or DAC Select
NC = NO CONNECT
Figure 20. SKT6, D-Type Connector Pinout
The analog output may be taken directly from the DAC or from a SHA at the output of the DAC. -13-
REV. B
AD7868
LK4, DAC Reference Selection COMPONENT LIST
The DAC reference may be connected to either the ADC reference output (RO ADC) or to the DAC reference (RO DAC).
LK5, ADC Internal Clock Selection
This link configures the ADC for continuous or noncontinuous internal clock operation.
LK6, DAC Updating
IC1 IC2, IC3 IC4, IC5, IC6, IC7, IC8, C1, C3, C5, C7 C9, C11, C13, C15 C17, C19, C23 C2, C4, C6, C8 C10, C12, C14, C16 C18, C20, C24 C21 C22 R1, R2, R4 R3, R5 R6 R7 LK1, LK2, LK3, LK4, LK5, LK6, LK7, LK8 LK9 SKT1, SKT2, SKT3, SKT4, SKT5 SKT6
AD7868 2X AD711 ADG201HS MC78L05 MC79L05 74HC4050 74HC221 10 F Capacitor
The DAC, LDAC input may asserted independently of the ADC CONVST signal or it may be tied to CONVST or it may tied to GND.
LK7, ADC Clock Source
0.1 F Capacitor 330 pF Capacitor 68 pF Capacitor 2 k Resistor 4.7 k Resistor 15 k Resistor 200 Resistor
This link provides the option for the ADC to use its own internal clock oscillator or an external TTL compatible clock.
LK8 Frame Synchronous Option
LK8 provides the option of tying the ADC RFS output to the DAC TFS input.
LK9 Transmit/Receive Clock Option
LK9 provides the option to connect the ADC RCLK to the DAC TCLK.
Shorting Plugs
BNC Sockets 9-Contact D-Type Connector
Figure 21. Silkscreen for the Circuit Diagram of Figure 19
-14-
REV. B
AD7868
Figure 22. Component Side Layout for the Circuit Diagram of Figure 19
Figure 23. Solder Side Layout for the Circuit Diagram of Figure 19
REV. B
-15-
AD7868
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
24-Pin Plastic (N-24)
24-Pin Cerdip (Q-24)
C1410-10-7/90
28-Pin Plastic SOIC (R-28)
-16-
REV. B
PRINTED IN U.S.A.

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